Three steps.
Zero ambiguity.

Correctness is not a claim. It is a continuous, automated proof. Every core follows the same three-step verification flow, from specification to CI.

Step 1

Golden Model

A Python reference model built directly to the NIST specification. It passes the official ACVP test vector set at every parameter level. The golden model IS the spec, frozen at the NIST standard version.

Language: Python · Anchor: NIST ACVP vectors · Version: Frozen at standard
Step 2

RTL Tie-Out

SystemVerilog RTL output is compared byte-for-byte against the golden model output. cocotb regressions run across the full parameter space. Every input/output pair must match exactly.

Tool: cocotb · Check: Byte-exact · Coverage: Full parameter space
Step 3

Continuous Validation

Self-checking testbenches run on every commit in CI. ACVP vectors are frozen at the NIST standard. No drift, no regressions. Any byte mismatch fails the build immediately.

Trigger: Every commit · Policy: Zero tolerance · Gate: Build fails on mismatch

What "Verified" means.

Precision in language matters. Here is exactly what we mean when we mark a core as "Verified," and what we do not mean.

"Verified" means all of the following:

Synthesizable SystemVerilog RTL that passes technology-independent synthesis. Self-checking testbenches passing across the full parameter space. Byte-exact tie-out to official NIST or RFC test vectors. Python golden reference model included and passing independently.

"Verified" does NOT mean:

A formal CAVP or FIPS 140-3 certificate. Timing or silicon sign-off. Foundry-certified or silicon-proven status. Dyber soft IP is foundry-portable RTL. It has not been submitted to CMVP, and no FIPS 140-3 validation is claimed. Timing closure and physical sign-off are engagement-specific activities that depend on the target process node and integration context.

Standard deliverables for all available soft IP

  • Synthesizable SystemVerilog RTL
  • Self-checking testbench(es)
  • Python golden reference model
  • cocotb regression suite
  • Synthesis scripts (technology-independent)
  • Integration and user guide

Verification artifacts included

  • ACVP test vector files (frozen at NIST standard version)
  • Golden model source with run instructions
  • cocotb regression log (pass/fail per vector)
  • Synthesis report (area, timing, technology-independent)
  • Coverage report (functional coverage metrics)
  • CI pipeline configuration

Vector-by-vector
verification status.

Every core in the portfolio, with its test vector source, vector count, and pass status. No exceptions, no partial passes.

Core Vectors Levels / Params Source Status
ML-KEM 180 / 180 All 3 levels. KeyGen checked vs ACVP tcId 26. NIST ACVP (FIPS 203) Pass
ML-DSA 210 / 210 All 3 levels. NIST ACVP (FIPS 204) Pass
SLH-DSA 72 / 72 6 SHAKE parameter sets (128/192/256 x small/fast). Full 17,088-byte signature tie-out. NIST ACVP (FIPS 205) Pass
AES-256 KAT 256-bit key. FIPS 197 Appendix C.3 Pass
AES-GCM KAT GCM mode. McGrew test vector Pass
AES-XTS 70+ vectors Full block (tcId 101), CTS (tcId 171), all 70 bit-level CTS cases. NIST ACVP Pass
SHA-2 KAT SHA-256, SHA-384, SHA-512. FIPS 180-4 Pass
SHA-3 / SHAKE 200+ vectors All output lengths. SHAKE-128, SHAKE-256. XKCP KATs + 200 randomized + hashlib KATs Pass
HMAC KAT HMAC-SHA-256. RFC 4231 TC1 / TC2 Pass
HKDF KAT HKDF-SHA-256. RFC 5869 TC1 Pass
Keccak 200+ vectors Keccak-f[1600] permutation. XKCP KATs + 200 randomized vectors Pass
CTR_DRBG KAT AES-256 CTR_DRBG. NIST DRBGVS vectors Pass
HMAC_DRBG KAT Instantiate, Reseed, Generate, Generate, 512B output. NIST ACVP hmacDRBG Pass
SP 800-90B Health Golden Random, stuck, biased, and boundary streams. Golden model across all stream types Pass
Standards Coverage
FIPS 203 FIPS 204 FIPS 205 FIPS 197 FIPS 180-4 FIPS 202 SP 800-90A SP 800-90B SP 800-90C SP 800-38D SP 800-38E RFC 2104 RFC 5869 IEEE 1619

Request verification
documentation.

Full ACVP scorecard, golden model source, cocotb regression logs, and synthesis reports available under NDA. Contact our team to discuss your verification requirements.