Hardware secure element IC with native post-quantum cryptography, designed as a drop-in replacement for legacy secure elements (Microchip ATECC608, NXP SE050, Infineon OPTIGA Trust M) in IoT, industrial, medical, and defense embedded applications. Proprietary DSCA-1 secure command processor with hardware-accelerated ML-KEM and ML-DSA in a tiny 5x5mm QFN-20 package.
16 protected key slots. Keys never leave the secure boundary. Hardware-enforced write-only key registers.
ML-KEM-512/768/1024 key encapsulation and ML-DSA-44/65/87 digital signatures. All FIPS 203/204 parameter sets.
Less than 10mW active, under 1uW deep sleep. Ideal for battery-powered and energy-harvesting IoT.
I2C (up to 1 MHz) and SPI (up to 10 MHz). APDU command interface compatible with ISO 7816-4.
| Parameter | Value |
|---|---|
| Package | QFN-20 (5x5mm, 0.5mm pitch, exposed pad) |
| Thermal Resistance (EP soldered) | 42 C/W (4-layer PCB, thermal pad soldered) |
| Interface | I2C (up to 1 MHz Fast Mode Plus), SPI Mode 0 (up to 10 MHz) |
| Supply Voltage | 2.0V to 3.6V (3.3V nominal, 2.5V supported) |
| Power (Active) | <10mW typical |
| Power (Deep Sleep) | <1uW |
| Temperature Range | -40 C to +85 C (Industrial) |
| Processor | DSCA-1, proprietary secure command architecture |
| Key Slots | 16 slots x 512 bytes (hardware-isolated NVM key store) |
| NV Storage | 16 KB eFlash (8 KB key store + 8 KB firmware) |
| TRNG | SP 800-90B compliant, ~2 Mbps conditioned output |
| Startup Time | 50 ms typ, 80 ms max |
| Algorithm | Standard | Description |
|---|---|---|
| ML-KEM-512/768/1024 | FIPS 203 | Lattice-based key encapsulation. All parameter sets supported. CNSA 2.0 requires ML-KEM-768 minimum. |
| ML-DSA-44/65/87 | FIPS 204 | Lattice-based digital signatures. All parameter sets supported. CNSA 2.0 requires ML-DSA-65 minimum. |
| Hybrid Modes | ECDH + ML-KEM and ECDSA + ML-DSA hybrid classical+PQC modes. |
| Algorithm | Standard | Description |
|---|---|---|
| ECC P-256 / P-384 | FIPS 186 | ECDSA sign/verify and ECDH key exchange. |
| AES-128 / 256 | FIPS 197 | CBC, CTR, GCM modes. Hardware AES round engine. |
| SHA-3 / SHAKE | FIPS 202 | SHA-3-256, SHAKE128, SHAKE256 via Keccak hardware core. |
| SHA-256/384/512 | FIPS 180 | SHA-2 family (firmware implementation). |
| HMAC / HKDF / CMAC | Various | HMAC-SHA-256/384, HKDF (SP 800-56C), CMAC-AES. |
| Hardware TRNG | SP 800-90B | True random number generator with continuous health testing. |
| Standard | Status |
|---|---|
| FIPS 140-3 Level 2 | Validation planned post-production silicon |
| Common Criteria | EAL4+ pathway planned (EN 419221-5) |
| CNSA 2.0 | ML-KEM-768/1024 + ML-DSA-65/87. CNSA mode enforces minimum parameter sets |
| FIPS 203 / 204 | All ML-KEM and ML-DSA parameter sets. ACVP test vectors passing |
| SP 800-90B | TRNG entropy source validation pending first-silicon characterization |
| IEC 62443 SL2 | Design target for industrial cybersecurity device identity |
| ISO/IEC 7816-4 | APDU command structure implemented |
QuantaSE enables post-quantum security for billions of IoT and embedded devices.
| Application | Description |
|---|---|
| Smart Meters | Utility companies mandating PQC by 2030. Secure meter authentication and encrypted readings. |
| Medical Devices | FDA cybersecurity requirements. Pacemakers, insulin pumps, patient monitors. |
| Industrial IoT | ICS/SCADA security for critical infrastructure. Sensor authentication and secure commands. |
| Consumer IoT | Smart locks, security cameras, home automation. Quantum-safe device identity. |
| Defense and Aerospace | CNSA 2.0 compliant device identity for military and government embedded systems. |
| Feature | QuantaSE | SEALSQ QS7001 | NXP SE050 | ATECC608B |
|---|---|---|---|---|
| ML-KEM | All param sets | Yes (shipping) | No | No |
| ML-DSA | All param sets | Yes (shipping) | No | No |
| Classical Crypto | ECC, AES, SHA-3 | ECC, AES | ECC, RSA, AES | ECC, AES, SHA-2 |
| TRNG | SP 800-90B | Not detailed | Yes | Yes |
| CNSA 2.0 | Yes | Yes | No | No |
| US-Sourced Silicon | Yes (GF USA) | No | No | No |
Competitor data from publicly available datasheets. SEALSQ and QS7001 are trademarks of SEALSQ Corp. ATECC608 is a trademark of Microchip Technology Inc. SE050 is a trademark of NXP Semiconductors. OPTIGA is a trademark of Infineon Technologies AG. All other trademarks are property of their respective owners.
| Platform | Details |
|---|---|
| Linux (Embedded) | I2C via i2c-dev + QuantaCore SDK; SPI via spidev. Yocto, Buildroot. |
| FreeRTOS / Zephyr | Native I2C/SPI HAL driver. Zephyr module: dyber,quantase. |
| Arduino / PlatformIO | QuantaSE Arduino library. AVR, SAM, ESP32 targets. |
| STM32 | QuantaSE STM32 HAL wrapper library. F4, F7, H7, U5 series. |
| Python | quantase_py via pip. Raspberry Pi, BeagleBone, desktop dev. |
| Pre-Silicon Simulator | libquantase_sim. Identical APDU interface as hardware. Docker available. |
| Part Number | Description | Package |
|---|---|---|
| QTSE-768-STD | QuantaSE Standard. ML-KEM-768 + ML-DSA-65 default modes | QFN-20 |
| QTSE-1024-STD | QuantaSE High-Assurance. ML-KEM-1024 + ML-DSA-87 default modes | QFN-20 |
| QTSE-GOV | QuantaSE Government. FIPS 140-3 L2 + CC EAL4+ | QFN-20 |
| QTSE-DEV-KIT | Developer eval kit. 5 units + breakout PCB + STM32 host + SDK | Kit |
Contact sales@dyber.org for volume pricing, availability, and detailed technical specifications.
Pilot program now accepting applications. Request evaluation hardware or talk to our engineering team.