Dedicated post-quantum cryptographic accelerator chiplet for integration with host processors and SoCs. Features Dyber's proprietary QLI (Quantum Lattice Interface).
| Form Factor | Chiplet / Bare Die |
| Die Area | ~25 mm² |
| Process Node | TSMC 7nm (target) |
| Host Interface | QLI (Quantum Lattice Interface) |
| Standard Interface | AXI4 / AXI4-Stream |
| NTT Cores | 8x parallel engines |
| Power | <2W TDP |
| Temperature | -40°C to +105°C |
| QLI Data Width | 128-bit / 256-bit configurable |
| QLI Clock | Up to 1.5 GHz |
| QLI Latency | <5ns chip-to-chip |
| AXI4 Bus | 64-bit data, 40-bit address |
| Interrupt | Level-sensitive, configurable |
| Debug | JTAG, trace port |
| Clock Input | External reference, internal PLL |
| Reset | Async reset with power-on sequence |
| Algorithm | Standard | Parameter Sets | Operations |
|---|---|---|---|
| ML-KEM | FIPS 203 | 512, 768, 1024 | KeyGen, Encapsulate, Decapsulate |
| ML-DSA | FIPS 204 | 44, 65, 87 | KeyGen, Sign, Verify |
| SLH-DSA | FIPS 205 | All variants (SHA-2 + SHAKE) | KeyGen, Sign, Verify |
| Hybrid | Composite | ML-KEM + ECDH, ML-DSA + ECDSA | Combined classical + PQC |
| QRNG | SP 800-90B | N/A | True quantum entropy generation |
QCORE-C1 integrates at the die level with host processors across all major architectures. One chiplet, multiple markets.
Co-packaged with Intel Xeon and AMD EPYC processors for datacenter PQC acceleration with minimal latency.
Integrated with ARM-based data processing units and smart network interface cards for inline PQC offload.
Ultra-low-power PQC for RISC-V embedded processors. Ideal for constrained devices and IoT gateways.
Companion chiplet for Xilinx Versal, Intel Agilex, and Lattice FPGA-based adaptive compute platforms.
QLI is Dyber's proprietary chip-to-chip interconnect, purpose-built for cryptographic workloads. It provides deterministic latency and constant-time data transfer to prevent timing side channels.
| Feature | Specification | Benefit |
|---|---|---|
| Constant-Time Transfer | Fixed cycle count per operation | Eliminates timing side channels at the interface level |
| Command Queue | 32-entry hardware FIFO | Burst operations without host CPU stalls |
| DMA Engine | Scatter-gather with IOMMU | Zero-copy transfers between host and chiplet memory |
| Error Correction | SEC-DED ECC on data bus | Silent error detection and correction |
| Power Management | Clock gating, power islands | Sub-milliwatt idle power consumption |
QCORE-C1 RTL running on AMD Versal evaluation boards. Full functional equivalence for software development and integration testing.
Complete physical design deliverables for chiplet integration. Includes timing models, power analysis, and packaging guidelines.
Production-tested bare die for multi-chip module assembly. Wafer-level and singulated die delivery options available.
Early access: QCORE-C1 FPGA prototypes are available now for qualified partners. Contact our hardware engineering team to discuss integration requirements and receive evaluation kits.
Pilot program now accepting applications. Request evaluation hardware or talk to our engineering team.