Verified, foundry-portable RTL for all three NIST post-quantum cryptography standards, plus the classical symmetric, entropy, and integration IP a complete secure product requires. Every core byte-exact against official NIST ACVP test vectors.
From the three NIST post-quantum standards to symmetric encryption, entropy generation, and secure integration, everything a quantum-safe SoC needs.
ML-KEM, ML-DSA, and SLH-DSA. The three NIST-standardized PQC algorithms as hardware IP for key establishment and authentication.
3 cores · All availableCombiners binding PQC to classical algorithms. Secure if either component holds. The safe path through the transition period.
2 cores · All availableShared, silicon-efficient math primitives reused across every algorithm core. Licensable individually for custom accelerators.
7 cores · All availableAES, SHA-2, HMAC, HKDF, and key wrapping. The classical primitives every secure product needs alongside PQC.
6 available · 1 roadmapQuantaSE-Q: chip-scale quantum RNG with SP 800-90 digital assurance back-end. Photonic entropy source plus three certified DRBGs.
8 cores · 7 available, 1 in designBoolean and arithmetic masking, shuffled sampling, power flattening, and fault-injection sensors.
RoadmapHardened RISC-V core with PQC ISA extensions, secure boot ROM, key-store controller, and PKCS#11 command interpreter.
RoadmapSecure AXI fabric, die-to-die PHY, PCIe controller, and CSR integration harness for SoC-level assembly.
RoadmapNIST FIPS 203 module-lattice key encapsulation. All three security levels (512/768/1024), runtime-selectable. Full KeyGen, Encaps, Decaps with FO transform.
NIST FIPS 204 module-lattice digital signatures. All levels (44/65/87), runtime-selectable. Full KeyGen, Sign with rejection loop, and Verify.
NIST FIPS 205 stateless hash-based signatures (SPHINCS+). Conservative, lattice-free alternative for defense-in-depth and long-lived roots of trust.
X-Wing-style hybrid KEM binding ML-KEM to X25519. Shared secret secure if either component remains unbroken. SHA3-256-based binding.
Composite ML-DSA + classical signatures. Domain-separated message representative with both-must-verify decision logic.
FIPS 202 permutation engine underlying all SHA-3, SHAKE, and cSHAKE operations. Verified vs XKCP KATs + 200 randomized vectors.
FIPS 202 extendable-output sponge with absorb, pad, and squeeze. Arbitrary output length for key derivation and sampling.
FIPS 202 fixed-output SHA-3 hash functions. All four output lengths. Verified vs hashlib including empty-message KATs.
FIPS 203 256-point forward/inverse NTT (q=3329). Parameterized single-butterfly datapath. Roadmap: R8 (area), R32 (4x throughput).
FIPS 203 NTT-domain base multiplication. Verified by composition: INTT of basemul equals the negacyclic convolution product.
FIPS 203 Parse: uniform sampler for the ML-KEM public matrix from a SHAKE-128 source. Constant-time rejection loop.
FIPS 203 SamplePolyCBD. Constant-time centered binomial distribution sampling for noise polynomials.
FIPS 197 encrypt + decrypt. Iterative single-block, 14 rounds at 1 per cycle, packed-constant S-box. Foundation for GCM/XTS/CTR.
SP 800-38D authenticated encryption (96-bit IV). GCTR + serial GF(2^128) GHASH. Byte-stream variant with AXI-Stream-lite interface.
IEEE 1619 / SP 800-38E storage encryption. Full-block + byte-aligned ciphertext stealing. Verified vs NIST ACVP enc+dec vectors.
FIPS 180-4 SHA-256/384/512 with streaming input and internal padding. Verified vs hashlib + FIPS 180-4 KATs.
FIPS 198-1 / RFC 2104 keyed-hash message authentication. Runtime lengths. Verified vs RFC 4231 test cases.
RFC 5869 extract-and-expand key derivation. Verified vs RFC 5869 TC1. For deriving session keys, key material expansion.
AES key wrapping with padding for secure key transport. Standards-compliant key encryption for HSM and key management applications.
Vacuum-fluctuation balanced-homodyne on GF Fotonix/45SPCLO. Entropy traceable to a quantum observable with live min-entropy bound.
Continuous Repetition-Count + Adaptive-Proportion tests with sticky alarms and output gating. Production variance monitor.
SP 800-90B section 3.1.5 vetted conditioning via SHAKE256. Back-pressure support. Production uses multi-core SHA3-256.
Windowed integer-variance monitor. Asserts quantum_ok when on/off variance ratio clears threshold. Division-free, measurable quantum entropy.
SP 800-90C sequencer: quantum-ratio-gated startup, health + quantum gated output, selectable DRBG output stage.
SP 800-90A section 10.2.1, no derivation function, 384-bit seedlen. The certifiable DRBG with published NIST DRBGVS vectors.
SP 800-90A HMAC-based DRBG. RTL byte-exact vs official NIST ACVP hmacDRBG vectors (Instantiate, Reseed, Generate, Generate).
SP 800-90A section 10.1.1 hash-based DRBG, 440-bit seedlen. SHA3-256 based for the QuantaSE-Q back-end.
First-order masking wrappers for PQC and symmetric cores. Shuffled sampling and power-flattening controller.
Voltage and clock glitch detectors, laser fault-injection sensors. FD-SOI body-bias native power flattening.
RISC-V core with PQC ISA extensions for cryptographic acceleration. Hardened against fault injection and side-channel attacks.
ML-DSA-65-anchored chain of trust from power-on through firmware to application. PQC-signed boot attestation.
Hardware PKCS#11 command processing for HSM and secure element applications. Standards-compliant cryptographic token interface.
Tamper interlocks, per-master access control, and crypto MMU for secure SoC-level interconnect.
Radix-16 native die-to-die physical layer for chiplet-based secure SoC architectures.
Every Dyber IP core is verified against the same test vectors a FIPS certification lab uses. Our methodology: golden model passes ACVP, then RTL is tied byte-exact to that golden. No gaps, no approximations.
Python reference model built to the NIST specification. Passes the official ACVP test vector set at every parameter level.
SystemVerilog RTL output compared byte-for-byte against the golden model. cocotb regressions run across the full parameter space.
Self-checking testbenches run on every commit. ACVP vectors are frozen at the NIST standard; no drift, no regressions.
From 90-day evaluation through perpetual production. No per-unit royalties on perpetual licenses.
| Tier | Description | Includes |
|---|---|---|
| Evaluation | 90-day evaluation with full RTL access for design-in assessment. | Full RTL, FPGA synthesis + simulation, technical support (email). No production rights. |
| Per-Design | Single SoC/ASIC design with production rights for one product line. | All eval deliverables + production rights (1 design), integration support, 12 months updates. |
| Volume | Multi-design license with per-unit royalty structure for high-volume. | Unlimited designs, volume-tiered royalties, dedicated FAE support, custom modifications. |
| Perpetual | Unlimited use across all products with no per-unit royalties. | Unlimited designs + volume, zero royalties, priority engineering support, joint roadmap input. |
All licenses include NDA-protected deliverables. Government/defense licensing available through Carahsoft.
Standard deliverables for all Available soft IP. Firm/hard IP (hardened netlist for a target node) is available on foundry enablement.
Foundry-portable RTL with synthesis scripts and constraint templates. Technology-independent by default.
cocotb regressions tied to ACVP vectors. Python golden reference model included for independent validation.
Complete user guide, interface specification, timing diagrams, and integration examples for SoC design-in.
Detailed specifications, block diagrams, and resource estimates for any IP core in the portfolio. NDA-protected evaluation available.