AES-256-XTS | Dyber IP Cores

Overview

AES-256 in XTS mode for disk and storage encryption. The core provides full-block encryption plus byte-aligned ciphertext stealing for partial final blocks. Variants include a byte-stream mode (runtime length) and a bit-level CTS mode for final blocks ranging from 1 to 127 bits.

Key Features

IEEE 1619 / SP 800-38E XTS mode
Full-block + byte-aligned ciphertext stealing
Byte-stream variant (aes_xts_stream) with runtime length
Bit-level CTS variant (aes_xts_bit) for final blocks 1 to 127 bits

Benefits

Complete storage encryption solution
Handles all edge cases including partial final blocks
Verified against all ACVP bit-level cases

Standards & Verification

Standards Compliance

IEEE 1619 NIST SP 800-38E

Verification

Verified vs NIST ACVP tcId 101 (full block), tcId 171 (CTS), enc+dec. Bit-level variant verified vs all 70 ACVP bit-level cases.

"Verified" means RTL byte-exact against official test vectors. It does not imply FIPS 140-3 certification or foundry sign-off.

Availability & Deliverables

Available Verified soft IP, ready for integration.

Standard Deliverables

Synthesizable SystemVerilog RTL
Self-checking testbench(es)
Python golden reference model
cocotb regression
Synthesis scripts
Integration/user guide

Firm/hard IP (hardened netlist for a target node) available on foundry enablement.

AES-256-XTS.