The classical symmetric, hash, MAC, and key-derivation primitives a complete secure product needs alongside PQC. Every one tied byte-exact to its standard test vectors.
Six verified cores covering AES-256 block encryption, authenticated encryption (GCM), storage encryption (XTS), SHA-2 hashing, HMAC message authentication, and HKDF key derivation. All delivered as synthesizable, foundry-portable SystemVerilog RTL.
FIPS 197 encrypt + decrypt; iterative single-block. 14 rounds, 1 per cycle, packed-constant S-box. Verified vs FIPS 197 App C.3 KAT. Foundation for GCM/XTS/CTR.
SP 800-38D AEAD (96-bit IV). GCTR + serial GF(2^128) GHASH; tag = AES(J0) XOR S. Byte-stream variant with AXI-Stream-lite.
IEEE 1619 / SP 800-38E storage encryption. Full-block + byte-aligned ciphertext stealing. Verified vs NIST ACVP. Variants: byte-stream, bit-level CTS.
FIPS 180-4 SHA-256/384/512. Streaming with internal padding. Verified vs hashlib + FIPS 180-4 KATs.
FIPS 198-1 / RFC 2104 keyed-hash MAC. Runtime lengths. Verified vs RFC 4231 TC1/TC2.
RFC 5869 extract-and-expand key derivation. Verified vs RFC 5869 TC1.
Every core in this family ships as soft IP with the same complete deliverable set. Foundry-portable, integration-ready, fully verified.
Soft IP, foundry-portable. All cores are delivered as synthesizable RTL that runs on any process node. Verification confirms algorithmic correctness against official NIST and RFC test vectors. It does not constitute a CAVP certificate or FIPS 140-3 validation. Firm and hard IP available on engagement.
Verified, foundry-portable symmetric and hash IP for your next secure design. All cores include complete testbenches, golden models, and integration documentation.