The three NIST-standardized post-quantum algorithms as hardware IP: a lattice KEM, a lattice signature, and a hash-based signature. Together, the complete quantum-safe primitive set for key establishment and authentication.
Each core implements one of the three NIST post-quantum cryptography standards as verified, foundry-portable SystemVerilog RTL.
FIPS 203 module-lattice key encapsulation, all security levels, ACVP-verified. ML-KEM-512/768/1024, runtime-selectable. Full KeyGen, Encaps, Decaps with FO transform and implicit rejection. Constant-time.
FIPS 204 module-lattice digital signatures, all levels, ACVP-exact. ML-DSA-44/65/87, runtime-selectable. Full KeyGen, Sign (rejection loop), Verify. Built from 11 verified primitive blocks.
FIPS 205 stateless hash-based signatures (SPHINCS+), conservative and lattice-free. Full KeyGen, Sign, Verify. 14 RTL modules (WOTS+, XMSS treehash, hypertree, FORS). Entirely SHAKE-based.
Every core in this family ships as verified, foundry-portable soft IP with a complete integration package.
Foundry-portable source, lint-clean, synthesis-ready for any target process or FPGA.
Constrained-random and directed testbenches that verify functional correctness against NIST test vectors.
Bit-exact Python implementation for independent cross-checking and integration testing.
Automated cocotb test suite for continuous integration and regression testing across environments.
Ready-to-run synthesis scripts for common EDA tool flows, with example constraint files.
Complete integration guide covering interfaces, timing, configuration parameters, and example SoC hookup.
Request a product brief for any core in this family, or contact us to discuss your integration requirements.