HMAC_DRBG (SHA-256) | Dyber IP Cores

Overview

HMAC-SHA-256 based deterministic random bit generator per SP 800-90A. RTL output is byte-exact against official NIST ACVP hmacDRBG test vectors covering the full Instantiate, Reseed, Generate, Generate sequence with 512-byte output. This core provides standards-compliant pseudorandom generation suitable for key generation, nonce production, and other security-critical applications requiring a hash-based DRBG construction.

Key Features

SP 800-90A HMAC_DRBG with SHA-256
Full Instantiate/Reseed/Generate sequence
NIST ACVP verified

Benefits

ACVP-verified for certification readiness
HMAC-based construction for applications preferring hash-based DRBG

Standards & Verification

Standards Compliance

NIST SP 800-90A

Verification

RTL byte-exact vs official NIST ACVP hmacDRBG (Instantiate, Reseed, Generate, Generate, 512 B output).

Note: "Verified" means RTL byte-exact against official test vectors. It does not imply FIPS 140-3 certification or foundry sign-off.

Availability & Deliverables

Available Available as verified soft IP.

Standard Deliverables

Synthesizable SystemVerilog RTL
Self-checking testbench(es)
Python golden reference model
cocotb regression
Synthesis scripts
Integration/user guide

Firm/hard IP (hardened netlist for a target node) available on foundry enablement.

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HMAC_DRBG (SHA-256).