Dyber QCORE-C1 Chiplet

Dyber Docs Hub Homepage QCORE-C1 Chiplet

Dedicated ML-KEM acceleration chiplet for OEM integration. 4mm squared die, SkyWater SKY130 process, with proprietary QLI die-to-die interface for multi-chiplet configurations.

Release Notes

Current silicon revisions, errata, and design updates for the QCORE-C1 chiplet.

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Quick Start

Get started with QCORE-C1 integration, from evaluation board setup to first cryptographic operation.

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Architecture

Detailed hardware architecture including NTT engine pipeline, memory subsystem, and QLI interface design.

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Developer Guide

Software development guide for QCORE-C1 including register programming, DMA operations, and firmware integration.

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Integration Guide

PCB design guidelines, power delivery, signal integrity, and thermal management for QCORE-C1 integration.

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QLI Protocol Specification

Complete specification for the Quantum Link Interface die-to-die protocol.

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QLI vs UCIe Comparison

Technical comparison between Dyber's QLI interface and the UCIe standard.

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Register Map

Complete register map and bit field definitions for the QCORE-C1 chiplet.

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Compliance Standards

FIPS 140-3, Common Criteria, and industry compliance documentation for QCORE-C1.

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Security

Security architecture, side-channel protections, and tamper resistance features.

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